1. Field of the Invention
The present invention relates to phase-locked loops (PLLs) and, more particularly, to digital filters used in digital PLLs.
2. Discussion of the Related Art
FIG. 1 schematically represents a conventional PLL structure. The PLL includes a voltage-controlled oscillator (VCO) 10 providing a frequency NF to a divide-by-N counter 12. A phase comparator 14 receives the output frequency F from divider 12 and a reference frequency Fref. The phase comparator 14 provides a phase error signal e to a filter 16 whose output c controls the VCO 10. In steady state, the phase and frequency of signal F are locked on signal Fref. In common applications, for example in the horizontal scanning of a television set, the frequency F to be obtained is approximately 15 kHz, the frequency NF is approximately 12 MHz (N=768), and filter 16 is a low-pass filter whose cut-off frequency is a few hundred Hz.
The present trend is to realize all the PLL elements in the form of digital circuits. This avoids the use of high value capacitors that are difficult to integrate, renders the elements programmable, and simplifies the design operations by allowing the use of standard blocks in MOS or CMOS technologies.
FIG. 2 represents a conventional digital low pass filter of the first order, with an integral and proportional correction function, that could be substituted for filter 16. The digital low-pass filter includes a register 20 that is fed back through an adder 21. The register 20 is clocked by the above signal F so that the output of adder 21 is loaded in the register at each period of signal F. A digital error signal E is provided to a second input of adder 21 through a multiplier 23 by a constant B, and to an adder 25 through a multiplier 27 by a constant A. The adder 25 also receives the output of adder 21 and provides a digital correction signal C intended to control a frequency synthesizer that replaces the VCO 10.
With this configuration, at a period k of signal F, value C is expressed by : EQU C(k)=I(k+1)+A E(k), with EQU I(k+1)=I(k)+B E(k),
where I(k) is the content of register 20 at period k of signal F. This corresponds to low-pass filtering of the first order.
To obtain a suitable operation of the PLL in the field of TV horizontal scanning, the register 20 must be large, for example of 22 bits, whereas it is sufficient that the phase error E is of 9 bits, and the correction signal C of 14 bits (signal C is then obtained from the 14 most significant bits of value I). The adders 21 and 25 must be 22-bit adders, each including 22 bit-to-bit or elemental adders, which involves a large silicon area.
Coefficients A and B are, for example, 7-bit numbers. Then, multipliers 23 and 27 provide a 16-bit result. These 16 bits do not necessarily correspond to the 16 most significant bits of register 20, which allows to introduce between the multipliers and the adders a constant dividing ratio by a power of 2 (the coefficients A and B are generally lower than 1, approximately 1/10 and 1/1000, respectively, for the horizontal scanning in a television set).
The 16-bit multipliers 23 and 27 also occupy a large area. If coefficients A and B are powers of two, multipliers 23 and 27 can be replaced by shift-left or shift-right circuits, whose shifting is determined by coefficients A and B. Such shift circuits occupy a smaller but still significant silicon area.